Digital detector of an analog signal

ABSTRACT

A circuit combination of integrated circuit (IC) digital devices for detecting an analog signal of a selected frequency and amplitude is disclosed. The circuit combination is a special-purpose digital filter of a predetermined bandwidth determined by the sample time T S  duration and the low F L  and high F H  frequencies of the passable analog signal frequency having a carrier frequency F A . The analog signal is initially tested for minimal amplitude and converted to a digital signal by a conventional comparator circuit. The pulses of the digital signal are counted over the sample time T S  and compared to the passable bandwidth: if the analog signal frequency F A  .[. (F L   ≦ F A   ≦  F H ).].   is within the bandpass, .Iadd.F L  ≦ F A  &lt; F H , .Iaddend. i.e., passable, a first binary signal is produced; alternatively, if the analog signal frequency F A  .[. (F L  &gt; F A   ≧   F H ).].   is without the bandpass, .Iadd.F L  &gt; F A  ≧ F H , .Iaddend. i.e., not passable, a second binary signal is produced. Sample times continue throughout the detection-comparing operation to ensure a continuous filtering process.

BACKGROUND OF THE INVENTION

Prior art detectors of an analog signal of a selected frequency andamplitude have been designed using an analog filter that passes only ananalog signal of the selected frequency and amplitude followed by afull-wave or half-wave rectifier and then a Schmitt trigger. Because ofthe availability of inexpensive and reliable digital circuits it isdesirable that previous analog techniques be replaced by digitaltechniques as proposed by the present invention.

SUMMARY OF THE INVENTION

In the digital filter of the present invention.Iadd., .Iaddend.an analoginput signal of a frequency F_(A) is initially tested for minimumamplitude and then converted to a binary digital waveform which is edgedetected to provide an output pulse for every cycle of the analog inputsignal. The first output pulse sets a sample time generator and thepulses are counted over the sample time T_(S). If the pulse count iswithin the bandpass at any time during the sample time T_(S) the counterand a binary decoder set a flip-flop to a True state. This flip-flop issampled at the end of the sample time and the True output is transferredto a storage element which is switched to the True condition. The Truecondition of the storage element after a one pulse width delay time thenresets the counter back to O. A time generator synchronizer driven bythe output of the edge detector is disabled if the condition of thestorage element is True. During the next successive sample time T_(S)the procedurre is repeated with the counter counting the number ofpulses from the edge detector. If the number of pulses counted is withinthe bandpass the binary decoder continues coupling a True condition tothe storage element with the counter reset as before and the timegenerator synchronizer being disabled. If during the next sample timeT_(S) the counter counts a number of pulses without the bandpass thebinary decoder couples a False output signal indicating that the analoginput signal is of a frequency outside the bandpass. This Falsecondition signal is delayed one pulse width to activate the timegenerator synchronizer in preparation for the next incoming pulse fromthe edge detector which incoming pulse initiates the sample timegenerator after which the detector-comparing operation is repeated.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of the special-purpose digital filter of thepresent invention.

FIG. 2, consisting of FIGS. 2a, 2b, is a logic level drawing of thespecial-purpose digital filter of FIG. 1.

FIG. 3 is a timing diagram illustrating the operation of thespecial-purpose digital filter of FIG. 1.

DESCRIPTION OF THE PREFERRED EMBODIMENT

With particular reference to FIG. 1 there is presented a block diagramof the special-purpose digital filter of the present invention, theelements thereof being illustrated in detail at their logic level inFIGS. 2a and 2b. The special-purpose digital filter of the presentinvention basically establishes a fixed sample time T_(S) during whichthe actual number N_(A) of cycles or pulses of a sampled signal arecounted. The number N_(A) is then compared to the minimum number N_(L)and the maximum number N_(H) of cycles or pulses that define thebandpass width of the filter. If within that range, i.e., .[.N_(L) ≦N_(A) ≦ N_(H) .]. .Iadd.N_(L) ≦ N_(A) < N_(H) .Iaddend. a first Truesignal is generated and if without the range, i.e., .[.N_(L) > N_(A) >N_(H) .]. .Iadd.N_(L) > N_(A) ≧ N_(H), .Iaddend.a second False signal isgenerated. The True and/or False signals are then set into a flip-flopand the flip-flop output is in turn clocked into the output storageelement (flip-flop) at the end of the sample period. Thus the Truecondition of the output storage element indicates that a signal meetingthe amplitude and frequency condition is present at the input to thecircuit. Conversely, the False condition indicates that the signal doesnot meet these conditions. Using the timing diagram of FIG. 3 to explainthe operation of the present invention illustrated in FIGS. 1, 2a, 2bcertain parameters shall be assumed by way of example to betterillustrate the operation of the present invention in its preferredembodiments of FIGS. 2a, 2b:

    F.sub.L = 900 Hz

    F.sub.H = 3000 Hz

    T.sub.S = 1/1.5 × .[.10.sup.-.sup.2 .]. .Iadd.10.sup.+.sup.2 .Iaddend. Hz = 6.67 × 10.sup.-.sup.3 sec.

Thus the sampled signal shall be sampled over a duration of 6.67 × 10⁻ ³sec. and if the sampled signal frequency F_(A) is within the bandpasswidth, i.e., .[.N_(L) ≦ N_(A) ≦ N_(H) .]. .Iadd.N_(L) = N_(A) < N_(H),.Iaddend.the filter shall .[.generated.]. .Iadd.generate .Iaddend.a Truesignal output and, alternatively, if the sample signal frequency iswithout the bandpass width the filter shall generate a False signaloutput.

Referring to the signal waveforms of FIG. 3, the analog signal A of afrequency F_(A) is coupled to comparator 10. Signal A is initiallycoupled to amplifier 10-1 which is an isolation and threshold detectorwhich compares signal A to a threshold level and if signal A is abovethe threshold level couples signal A to converter 10-2. Converter 10-2converts the analog signal A of a frequency F_(A) to the digital signalB. The digital signal B is then coupled to edge detector 20 whichproduces, as an output, signal C which consists of a single shortduration output pulse for every complete input cycle of signal B. SignalC is, in turn, coupled in parallel to counter 30 and sample timecontroller 40. At binary counter 30-1 the pulses of signal C, beginningat time t₀, are counted with the running total count being decoded bybinary decoder 30-2 which, in turn couples a decoder True signal tolower band edge detector 30-3 .[.if.]. .Iadd.when .Iaddend.the decodedbinary count is equal to the lower bandpass.Iadd., i.e., when N_(A) =N_(L), .Iaddend.and a decoder False signal to upper band edge detector30-4 .[.if.]. .Iadd.when .Iaddend.the decoded binary count is.[.above.]. .Iadd.equal to .Iaddend.the upper bandpass.Iadd., i.e., whenN_(A) = N_(H). .Iaddend.At sample time controller 40 the first pulse ofsignal C triggers time generator synchronizer 40-1 coupling a singleshort duration pulse to synchronizer edge detector 40-2 that couples thesignal D to the sample time generator 60. Signal D triggers time basegenerator 60-1 to generate signal E which is, in turn, coupled to timebase leading edge detector 60-2 which generates as an output therefromsignal F which is coupled to edge triggered bistable multivibrator orflip-flop 80-1 of memory element 80 by way of inverter 80-2 and to timebase trailing edge detector 70-1 which generates an output signal G.Signal G resets the binary counter 30-1 to O and through NAND gate 70-3and inverter 70-4 sets bistable multivibrator or flip-flop 70-2. At thistime, edge triggered bistable multivibrator 80-1 of memory element 80 iscoupling a relatively low level False state of output signal O to anoutput line 80-3 and as a first input to NAND gate 50-1 of synchronizercontroller 50.

Counter 30 is set to a bandpass of a count of 6 - 20, .Iadd.i.e., 6≦N_(A) < 20, .Iaddend.and, accordingly, at the count of 6 binary decoder30-2 couples a True decode pulse to lower band edge detector 30-3 which,in turn couples decode True signal H to bistable multivibrator 70-2causing it to change its state. Binary counter 30-1 continues countingthe subsequent pulses 7 - 19 of signal C causing lower band edgedetector 30-2 to remain in its previously set True state.

At the end of the sample time T_(S) time base generator 60-1 couples thesecond pulse of signal E to time base leading edge detector 60-2 which,in turn, couples the second pulse of signal F to edge triggered bistablemultivibrator 80-1 by way of inverter 80-2 which gates the state ofbistable multivibrator 80-2 therein causing memory element 80 to coupleto its output line the relatively high level True state of output signalO and through NAND gate 70-3 and inverter 70-4 causes bistablemultivibrator 70-2 to change to a False state. The concurrentapplication of the signal G and signal O at NAND gate 50-1 disables thetime generator synchronizer 40-1.

Under the above described conditions the input signal A has been assumedto be within the bandpass of a pulse count of 6 - 20, .Iadd.i.e., 6 ≦N_(A) < 20, .Iaddend.e.g., F_(L) = 900 Hz, F_(H) = 3000 Hz at a sampletime T_(S) of 6.67 × 10⁻ ³ sec. If the count had been .Iadd.equal to or.Iaddend.greater than 20.Iadd., i.e., N_(A) ≧ 20, .Iaddend.at time t₁,e.g., after sample time T_(S) binary decoder 30-2 would have coupled theappropriate signal to upper band edge detector 30-4 which, in turn,would have coupled a decode False pulse to NAND gate 70-3 and inverter70-4 which, in turn, would have changed the state of bistablemultivibrator 70-2 which False state of bistable multivibrator 70-2would have caused edge triggered bistable multivibrator 80-1 to couplethe low level False state of output signal O to output line 80-3 whengated by inverter 80-2. Alternatively, if the count had been less than6.Iadd., i.e., 6 > N_(A), .Iaddend.at time t₁, e.g., after sample timeT_(S), binary decoder 30-2 would not have coupled any True decode signalto lower band edge detector 30-3 whereby no high level pulse of signal Hwould have been coupled to bistable multivibrator 70-2 causing edgetriggered bistable multivibrator 80-1 to continue coupling therelatively low level False state of output signal O to output line 80-3of memory 80 when triggered by inverter 80-2. With the output signal Acontinuing to be of a frequency F_(A) within the bandpass, memoryelement .[.A.]. .Iadd.80 .Iaddend.continues coupling its relatively highlevel True state of output signal O to its output line 80-3. However, asat the end of the sample time T_(S) at time t₁ the second pulse ofsignal F from time base trailing edge detector 70-1 has reset binarycounter 30-1 to O the above described sequence repeats itself testingthe incoming signal A for its frequency F_(A) to determine, if at anytime, it is within or without the bandpass and to provide acorresponding high level True state or low level False state of outputsignal O on its output line 80-3.

What is claimed is:
 1. A digital detector of an analog signal,comprising:means receiving an input analog signal of a frequency F_(A)for generating a digital signal of a frequency F_(A) therefrom; countingmeans coupled to said digital signal for counting the number of pulsesN_(A) thereof during a preset sample time T_(S) and generating a decodeTrue signal if the counted number of pulses is equal to or greater thana preset low N_(L) number of pulses and generating a decode False signalif the counted number of pulses is .Iadd.equal to or .Iaddend.greaterthan a preset high N_(H) number of pulses for defining a presetbandwidth .[.N_(L) ≦ N_(A) ≦ N_(H) .]. .Iadd.N_(L) ≦ N_(A) < N_(H).Iaddend.; an output flip-flop for generating as the alternative outputsignals an output True signal or an output False signal indicating thatsaid counting means has counted a number of pulses N_(A) of said digitalsignal that is within or without, respectively, said preset bandwidth; adecoder flip-flop responsively coupled to said decode True signal andsaid decode False signal for storing a decoder True signal or a decoderFalse signal; means gating the decoder True signal or the decoder Falsesignal from said decoder flip-flop into said output flip-flop forstoring and generating an output False signal or an output True signal,respectively, on a detector output line therefrom.
 2. A digital detectorof an analog signal, comprising:means receiving an input analog signalof a frequency F_(A) for generating a digital signal comprising a seriesof short duration pulses of a frequency F_(A), one pulse for every cycleof said input analog signal; sample time base generator means coupled tosaid digital signal for generating, when effected by a first pulse ofsaid digital signal, a sample time signal comprising a first sample timepulse and after the sample time T_(S) a second sample time pulse;counting means coupled to said digital signal for counting the number ofpulses N_(A) thereof during said sample time T_(S) and generating adecode True signal if the counted number of pulses is equal to .Iadd.orgreater than .Iaddend.a preset low N_(L) count and generating a decodeFalse signal if the counted number of pulses is .Iadd.equal to or.Iaddend.greater than a preset high N_(H) count for defining a presetbandwidth .[.N_(L) ≦ N_(A) ≦ N_(H) .]. .Iadd.N_(L) ≦ N_(A) <N_(H).Iaddend. ; means coupling said sample time signal to said countingmeans for resetting said counting means to a zero count upon receipt ofsaid first sample time pulse; output memory means for generating as thealternative output signals an output True signal or an output Falsesignal indicating that said counting means has counted a number ofpulses of said digital signal that is within or without, respectively,said preset bandwidth; decoder memory means coupled to said decode Truesignal and said decode False signal for coupling a decoder True signalor a decoder False signal to said output memory means; means couplingsaid second sample time pulse to said output memory means for gating thedecoder True signal or the decoder False signal from said decoder memorymeans into said output memory means and coupling an output True signalor an output False signal, respectively, therefrom on a detector outputline.
 3. The digital detector of claim 2 further including:gating meanscoupled to said detector output line and said sample time base generatormeans for generating a new sample time signal when affected by an outputFalse signal. .Iadd.
 4. A bandpass digital filter, comprising: means forreceiving an input signal of a frequency F_(A) ; means responsivelycoupled to said receiving means for counting the number of pulses N_(A)of said input signal during a sample time T_(S) ; means responsivelycoupled to said counting means for generating a first signal if thecounted number of pulses N_(A) is equal to or greater than a low N_(L)number of pulses and for generating a second signal if the countednumber of pulses N_(A) is equal to or greater than a high N_(H) numberof pulses for defining a bandpass N_(L) ≦ N_(A) < N_(H) ; meansresponsively coupled to said bandpass defining means for generating awithin bandpass output signal only when said first signal but not saidsecond signal was coupled thereto. .Iaddend..Iadd.
 5. A bandpass digitalfilter, comprising: means for generating a sample time signal of aduration T_(S) ; means for receiving an input signal of a frequencyF_(A) ; means responsively coupled to said sample time signal generatingmeans and said input signal receiving means for counting the number ofpulses N_(A) of said input signal during said sample time T_(S) ; meansresponsively coupled to said counting means for generating a firstsignal when the counted number of pulses N_(A) is equal to a low N_(L)number of pulses and a second signal when the counted number of pulsesN_(A) is equal to a high N_(H) number of pulses for defining a bandpassN_(L) ≦ N_(A) < N_(H) ; means responsively coupled to said bandpassdefining means for generating a within bandpass output signal only ifsaid first signal but not said second signal was coupled thereto..Iaddend..Iadd.
 6. A bandpass digital filter, comprising: sample timingmeans for generating successive sample timing pulses, successive ones ofwhich define successive sample times of a fixed duration T_(S) ; inputmeans for receiving an input signal of a frequency F_(A) ; countingmeans responsively coupled to said sample timing means and said inputmeans for counting the number of pulses N_(A) of an input signal duringeach of the successive ones of said sample times T_(S) ; detector meansresponsively coupled to said counting means for generating a lower bandedge detector signal when the counted number of pulses N_(A) is equal toa preset low N_(L) number of pulses and an upper band edge detectorsignal when the counted number of pulses N_(A) is equal to a preset highN_(H) number of pulses for defining a preset bandpass N_(L) ≦ N_(A) <N_(H) ; output signal means responsively coupled to said detector meansfor generating a within bandpass signal only when said lower band edgedetector signal but not said upper band edge detector signal is coupledthereto during any one of said successive sample times T_(S)..Iaddend..Iadd.
 7. The bandpass filter of claim 6 wherein said outputsignal means includes a memory means; means coupling said sample timingmeans to said memory means for setting said memory means into an initialFalse state at the beginning of each one of said successive sample timesT_(S). .Iaddend..Iadd.
 8. The bandpass filter of claim 7 wherein saidoutput signal means includes means for coupling said lower band edgedetector signal to said memory means for setting said memory means intoa True state from said initial False state. .Iaddend..Iadd.
 9. Thebandpass filter of claim 8 wherein said output signal means includesmeans coupling said upper band edge detector signal to said memory meansfor setting said memory means back into said initial False state fromsaid True state. .Iaddend..Iadd.
 10. A bandpass digital filter,comprising: means for generating successive sample time signals thatdefine successive sample times that are each of a fixed duration T_(S) ;means for receiving an input signal of a frequency F_(A) ; meansresponsively coupled to said successive sample time signal generatingmeans and said input signal receiving means for counting the number ofpulses N_(A) of said input signal during each one of said successivesample times; means responsively coupled to said counting means forgenerating a first signal when during a first one of said successivesample times the counted number of pulses N_(A) is equal to a low N_(L)number of pulses, i.e., N_(L) = N_(A), and for generating a secondsignal when during said first one of said successive sample times thecounted number of pulses N_(A) is equal to a high N_(H) number ofpulses, i.e., N_(A) = N_(H), said first and second signals defining abandpass width N_(L) ≦ N_(A) < N_(H) ; means responsively coupled tosaid bandpass width defining means for generating a within bandpassoutput signal during a second one of said successive sample times nextfollowing said first one of said successive sample times only when saidfirst signal but not said second signal was coupled thereto during saidfirst one of said successive sample times. .Iaddend.